Split electrode gate trench power device

ABSTRACT

A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.

RELATED APPLICATION

This application is based on and claims the benefit of U.S. ProvisionalApplication Ser. No. 60/702,919, filed on Jul. 27, 2005, entitled SPLITELECTRODE GATE TRENCH MOSFET STRUCTURE AND PROCESS AND SF₆ ETCH PROCESS,to which a claim of priority is hereby made and the disclosure of whichis incorporated by reference.

FIELD OF THE INVENTION

The present invention related to power semiconductor devices and moreparticularly to MOSgated trench type power semiconductor devices.

BACKGROUND OF THE INVENTION

Power semiconductor devices are used prevalently in power managementapplications, for example, power converters and power supplies. In manyapplications, efficiency of the power converter is strongly related tothe efficiency of the power semiconductor device used therein. To obtaina higher efficiency, the current carrying capability of thesemiconductor device must be improved which reduces its on resistance.To increase the current carrying capability of, for example, a trenchtype MOSgate device the pitch (the cell to cell distance) can bereduced. However, to reduce the pitch, the gate charge must also bereduced to reduce Qgd.

It is desirable to improve the current carrying capability of a powersemiconductor device without having adverse effects on Qgd.

SUMMARY OF THE INVENTION

A power semiconductor device according to the present invention includesa semiconductor body having a drift region of one conductivity, and abase region of another conductivity, a gate trench extending at leastthrough the base region, gate insulation liner lining at least thesidewalls of the gate trench, a gate electrode adjacent each gateinsulation, an insulation block interposed between the gate electrodesand adjacent each gate electrode, a conductive regions of the oneconductivity adjacent the gate trench, and a first power electrodeelectrically connected to the conductive regions.

According to one aspect of the present invention, gate electrode mass isreduced (reducing gate charge), and the overlap between the gateelectrode and the drain is also reduced, thus reducing Qgd. As a result,prior art solutions requiring, for example, a thick oxide at the bottomof the trench may be eliminated.

A device according to the present invention may further include aconnector connecting the gate electrodes.

To reduce the resistance of the gates, each gate electrode can include asilicided portion that makes electrical contact with a gate runner,and/or the gate electrodes are made proud of the semiconductor body.

Other features and advantages of the present invention will becomeapparent from the following description of the invention which refers tothe accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a single cell of a powersemiconductor device according to the first embodiment of the presentinvention.

FIGS. 2A-2J illustrate selected steps in the fabrication of a powersemiconductor device according to the present invention.

FIG. 3 illustrates a cross-sectional view of a single active cell of adevice according to the second embodiment of the present invention.

FIG. 4 illustrates a cross-sectional view of a single active cell of adevice according to the third embodiment of the present invention.

FIGS. 5A-5D illustrate selected steps in the process for fabrication ofa device according to the third embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Referring to FIG. 1, an active cell of a power device, which ispreferably a power MOSFET, includes a gate trench 10 formed in asemiconductor body 12, for example, an epitaxially formed silicon. Gateoxide liner 14 lines at least each sidewall of trench 10, and preferablyalso the bottom thereof. A gate electrode 16 is disposed inside trench10 adjacent gate oxide 14. In the first embodiment of the presentinvention, gate electrode 16 has a π-shaped cross-section with twovertically oriented fingers 16′, and a horizontally oriented connector16″, linking the two opposing and spaced fingers 16′. The space betweenfingers 16′ is filled with an insulation block 18. Gate electrode 16 ispreferably made of conductive polysilicon having the top thereofsilicided 20 in order to increase the conductivity thereof. Silicidingis particularly advantageous in reducing Rg (gate resistance) when gatetrenches 10 are narrowed. To be specific, in a device according to thepresent invention, at least one gate runner is provided to connect thegate electrodes to one another. In the preferred embodiment, thesilicided portions are connected to the runner in order to reduce theresistance between the runner and the gate electrodes, thereby reducingthe overall Rg of the device.

A power MOSFET according to the preferred embodiment includes driftregion 24 of one conductivity (e.g., N-type), base region 22 of anotherconductivity (e.g., P-type), source regions 26 of the one conductivity,source electrode 28 which is ohmically connected to source regions 26,and shorted to base region 22 through high conductivity contact regions30 of the same conductivity as base region 22, but insulated from gateelectrode 16 by an insulation cap 32. It should be noted that driftlayer 24 is formed preferably over a silicon substrate 34 of the oneconductivity. Drain electrode 36 is ohmically connected to substrate 34,whereby current travels vertically from source electrode 28 to drainelectrode 36 when a channel is formed in base region 22 adjacent trench10 between source region 26 and drift region 24 upon application of atleast the threshold voltage to gate electrode 16.

Returning to FIGS. 2A-2J, to fabricate a device according to the firstembodiment of the present invention, a semiconductor body 12, whichincludes source region 26, base region 22, and drift region 24 is maskedwith a hard mask 38 (e.g., Si₃N₄ mask). Hard mask 38 includes openings40, which define areas in semiconductor body 12 to be trenched.Thereafter, a gate trench 10 is formed in semiconductor body 12 at leastthrough base region 22 using any suitable etching method to obtain thestructure shown in FIG. 2A.

Next, the sidewalls and the bottom of trench 10 are oxidized using anyknown method to form gate insulation/oxide 14 thereon to a thickness ofpreferably 500 A, as illustrated by FIG. 2B. Thereafter, a layer ofpolysilicon 40 is deposited to cover at least gate insulation 14 as seenin FIG. 2C, and then any excess polysilicon 40 is removed from at leastthe bottom of trench 10 (leaving oxide behind) leaving polysiliconliners 42 along the sidewall of trench 10, as illustrated by FIG. 2D.

Next, an oxide filler 44 is deposited to fill at least trench 10 (FIG.2E), and then a portion thereof is removed to leave insulation/oxideblock 18 at the bottom of trench 10 as seen in FIG. 2F.

Next, polysilicon 46 is deposited over oxide block 18 to connectpolysilicon liners 42 as illustrated by FIG. 2G. Polysilicon 46 is thensilicided to form silicide body 20, as illustrated by FIG. 2H. Note thatas a result, gate electrode 16 is formed in this step.

Next, hard mask 38 is removed (FIG. 2I), and a preferably low densityoxide body 46 (e.g., TEOS) is deposited over at least silicide body 20.Thereafter, conventional steps are carried out to obtain a device asillustrated by FIG. 1. It should be appreciated that although only asingle active cell and a process for forming a single active cell areillustrated by FIGS. 1, 2A-2J, in a device according to the presentinvention a plurality of active cells would be formed simultaneously.Thus, the present invention should not be understood to be limited to asingle active cell.

Referring next to FIG. 3, in a device according to the secondembodiment, the sidewalls of trench 10 are tapered. Moreover, gateelectrode 16 is proud of gate trench 10, i.e., extends outside of trench10 above the top surface of semiconductor body 12.

To fabricate a device according to the second embodiment, trench 10 isformed to have tapered sidewalls instead of vertical sidewalls. Toobtain the proud gates, polysilicon 44 (FIG. 2F) is left inside opening40 of mask 38, silicided, and then when mask 38 is removed, gateelectrode 16 is left proud of trench 10.

Referring to FIG. 4, a device according to the third embodiment alsoincludes gate trench 10 with preferably tapered sidewalls. However,unlike the first and the second embodiments, gate electrode 16 does notinclude connector portion 16″. Thus, the third embodiment includes onlygate fingers 16′ (or gate liners 16′). Furthermore, a thick oxide body50 is disposed at the bottom of gate trench 10 extending below gateliners 16′. Thus, in a modified process, after forming gate oxide 14 onthe tapered sidewalls of a gate trench 10, a trench oxide 50 is formedat the bottom of trench 10 as illustrated by FIG. 5A. (Note that in aprocess for fabricating the second and third embodiments, a polysiliconbody 51 is optionally formed over semiconductor body 12 and under hardmask 38. Polysilicon body 51 is used to improve hard mask 38.Specifically, in order to prevent the undue straining of hard mask 38polysilicon 51 is used, which allows one to build up and create the“proud” structure without inducing undue stress.)

Next, polysilicon gate liners 16′ are found adjacent the sidewalls oftrench 10 by polysilicon deposition and etching. The polysilicon gatelines 16′ may be made proud by extending beyond trench 10, andoptionally (or alternatively) silicide 20 to reduce Rg. Thereafter, asillustrated by FIG. 5C, oxide is deposited inside the trench therebyforming oxide/insulation block 18.

After the oxide deposition, hard mask 38, and underlying polysilicon 51are removed to expose the silicon below, and source regions 26, regions30, base region 22 are formed through conventional implementation anddiffusion steps followed by conventional steps to form electrodes 28 and36 to obtain a device according to the third embodiment.

Although the present invention has been described in relation toparticular embodiments thereof, many other variations and modificationsand other uses will become apparent to those skilled in the art. It ispreferred, therefore, that the present invention be limited not by thespecific disclosure herein, but only by the appended claims.

1. A power semiconductor device, comprising: a semiconductor bodyincluding a drift region of one conductivity, and a base region ofanother conductivity; a gate trench extending at least through said baseregion; gate insulation liner lining at least the sidewalls of said gatetrench; a gate electrode adjacent each said gate insulation; aninsulation block interposed between said gate electrodes and adjacenteach gate electrode; a conductive regions of said one conductivityadjacent said gate trench; and a first power electrode electricallyconnected to said conductive regions.
 2. The device of claim 1, furthercomprising a connector connecting said gate electrodes.
 3. The device ofclaim 1, further comprising a gate runner electrically connected to gateelectrodes, wherein each said gate electrode includes a silicidedportion that makes electrical contact with said gate runner.
 4. Thedevice of claim 1, wherein said gate electrodes are proud of saidsemiconductor body.
 5. The device of claim 1, wherein said device is apower MOSFET.
 6. The device of claim 1, further comprising an insulationbody at the bottom of said gate trench, said insulation body beingthicker than said gate insulation liners.
 7. The device of claim 1,wherein said gate insulation liners, said insulation block, and saidinsulation body are comprised of an oxide.
 8. The device of claim 1,further comprising a gate runner, wherein each said gate electrodes areelectrically connected to said gate runner through a low resistivitysilicided portion.
 9. The device of claim 1, further comprising asilicided connector connecting said gate electrodes to a gate runner.10. The device of claim 1, further comprising a substrate of said oneconductivity, said semiconductor body being disposed on said substrateand further comprising a second power electrode electrically connectedto said substrate.
 11. The device of claim 10, wherein said first powerelectrode is a source electrode, said second power electrode is a drainelectrode, and said conductive regions are source regions.
 12. A methodof fabricating a power semiconductor device, comprising: trenching asemiconductor body that includes a drift region and a base regionadjacent said drift region; oxidizing at least the sidewalls of saidtrench to form gate liners adjacent said sidewalls; covering saidoxidized sidewalls with an electrically conductive material to form gateliners; and depositing an insulation block between said gate liners andadjacent each gate liner.
 13. The method of claim 12, further comprisingforming an insulation body at the bottom of said trench, said insulationbody being thicker than said gate liners.
 14. The method of claim 12,said conductive material comprises conductive polysilicon.
 15. Themethod of claim 12, further comprising linking said gate liners with aconductive connector.
 16. The method of claim 12, further comprisingconnecting said gate liners to a gate runner through a silicided gateportion.
 17. The method of claim 12, wherein said gate liners are proudof said semiconductor body.
 18. The method of claim 15, wherein saidconnector is proud of said semiconductor body.